1. Field of the Invention
The present invention concerns a semiconductor memory device, and more particularly a circuit for testing a semiconductor memory device operating at a high frequency.
2. Description of the Related Art
Solid state memory devices have evolved in generally two directions: the first is to increase the memory density and the second is to increase the bandwidth, i.e., the operating speed, of the device. These two kinds of development require increased test time and improved test equipment thus increasing the cost of testing as well as degrading the test yield of the memory device.
Referring to FIG. 1, conventional test equipment comprises a mode register 10, a latency controller 20 for receiving an external clock signal CLK and the output of the mode register 10, and an internal column address generator 30 for receiving the external lock signal CLK, the output of the mode register 10, and the address Ai. The conventional test equipment shown in FIG. 1 also includes a column address decoder 40 synchronized with the external clock signal CLK for decoding the output signal CAi of the internal column address generator 30, a memory cell 50 for reading out or writing in data responsive to the output of the column address decoder 40, and an input/output control unit 60 for receiving the external clock signal CLK and the output latency CL of the latency controller 20 to control the data input/output of the memory cell. The data output buffer 70 receives the outputs of the input/output control unit 60 and latency controller 20 and transfers the output of the input/output control unit 60 having a certain level to the data input/output pin DQ. The data input buffer 80 transfers the data of the data input/output pin DQ to the data input/output control unit 60.
Such conventional test equipment is designed to test high density memory devices and can be modified slightly to test newly developed high density memory devices. However, the conventional test equipment shown in FIG. 1 is unsuited for testing high speed memory devices which ordinarily require specially designed test equipment having adequate bandwidth.